By Kate Yuan

New opportunities have emerged for the EDA companies in the Chinese mainland given EDA’s crucial role in the large-scale industrialization of 3D IC, a JW Insights article said on October 17.

The 3D IC, which is composed of multiple bare chips/chiplets by 2.5D/3D stacking, can realize the "decoupling" of each on-chip module of traditional SoC. It is able to comprehensively optimize chip functions, performance, costs, and development cycles, which has also been verified by the pioneering products from companies like AMD.

UMC, the world's third largest foundry, has also made new moves in 3D IC recently after TSMC and Samsung. It announced to team up with EDA giant Siemens Mentor to provide customers with 3D IC planning, assembly verification and parasitic extraction workflows required for chip-on-wafer (C2W) and wafer-on-wafer (W2W) bonding.

UMC's action may be considered to pave the way for the 3D IC hybrid-bonding process mentioned in its annual report and planned to be launched in 2023.

Chinese players have also actively deployed in related fields. The UCIe consortium, which aims to create an industry standard for the interconnection between chiplets, has now taken in more than 10 members from China’s mainland, including JCET Group(长电科技） and TF Microelectronics （通富微电).

However, the basic technologies and potential customers of the new forms of products are still largely in the hands of global giants. For companies in China’s mainland, incremental opportunities are often seen but not easy to seize. Avoiding a larger gap with top players may be more important.

Currently, companies from China’s mainland have made some achievements in key technologies such as TSV, thinning, and bonding required for 3D ICs. However, in addition to developing key technologies, they must also pass the certification of EDA tools to create the bridge between design companies and manufacturing and packaging and testing companies. Because 3D ICs require closer collaboration among companies in chip logic design, physical design, manufacturing, and packaging.

Xie Zhonghui, chief market strategy officer of X-EPIC (芯华章), told JW Insights that the chiplet concept contains many new technologies related to EDA, and the design verification of chiplets also sets new requirements for traditional EDA. Especially the verification technology and tools have become one of the bottlenecks in the development of chiplets.

Compared with foundries such as UMC, the R&D of 3D IC technology is happening more in Chinese packaging and testing companies, which still relatively lag behind for their customer-centric design processes, tools, and system construction.

An EDA industry insider said that the reason for this situation, on the one hand, is that customers with such needs are fewer in China. On the other hand, the commercial EDA toolchain for 3D ICs is incomplete.

Considering the critical significance of the EDA ecosystem, Chinese players should make a difference in this field. The incomplete 3D IC design methodology and toolchain have also created opportunities for local EDA manufacturers.

Pan Peichen, CEO of China’s EDA developer LEDA Technology (立芯软件) pointed out, “3D IC designers want a design environment integrating all the required functions, and local EDA providers can give play to their competitiveness in single tools and unite with the help of unified standards.

Pan also analyzed the far-reaching impact of 3D IC on the EDA/IP business ecosystem. “When hard IP becomes a physical form of chiplets, it will help more system companies and IT companies to set foot in IC design. Some chip companies may transform to one-stop solution providers by offering customers with verified base dies and a rich combination of self-developed or third-party functional chiplets,” he added, “This will further lower customers’ threshold to start businesses, and it is in line with the data center needs of many Internet giants.”