By Greg Gao

(JW Insights) Aug 4 -- JCET Group(长电科技), the largest Outsourced Semiconductor Assembly and Test (OSAT) company in China’s mainland, has leveraged Chiplet technologies to achieve high-volume production of packaging for 4 nm chips for its customers, the company shared this information in its investor relationship management platform of the Shanghai Stock Exchange on August 4.

Recently, on the platform, a shareholder asked JCET whether the company has a layout for CoWoS (Chip-on-Wafer-on-Substrate), a 2.5D wafer-level multi-chip packaging technology that incorporates multiple dies side-by-side on a silicon interposer in order to achieve better interconnect density and performance.

JCET responded that the company has relevant deployments in the high-performance packaging field. The company has already introduced the technology platform for multidimensional fan-out integration (XDFOI) tailored to the 2.5D and 3D packaging, covering various packaging integration solutions, including 2D, 2.5D, and 3D, and has achieved mass production. 

This technology is a high-density, multi-fan-out type packaging solution aimed at Chiplets with advanced heterogeneous integration capabilities, already equipped for 4nm chips and Chiplet advanced packaging technology mass production. The company has begun providing high-performance advanced packaging solutions tailored to small chip architectures to both domestic and overseas customers and has promptly allocated corresponding production capacity to them.

Founded in 1972 and listed on Shanghai Stock Exchange in 2003, JCET is based in Jiangyin, eastern China’s Jiangsu Province. As a leading global provider of Integrated Circuit (IC) backend manufacturing and technology services, it has a comprehensive portfolio that covers a wide spectrum of semiconductor applications, such as smartphones, communications, computing, and automobile, through advanced wafer-level packaging.